Basic dynamic scaling voltage DVS processing modules exist in the prior art, for example the Intel™ Speedstep™ technology applied to many laptop computers in which the processor is allowed to enter a “sleep” mode when not in use in order to reduce power consumption from the battery. Recently processing modules have emerged which are able to operate at a number of different voltage and frequency or clock speed rates. Power consumption in a processor is a function of both voltage and clock speed or frequency, and as is known a quadratic reduction in power consumption can theoretically be achieved by reducing both these parameters. Transmeta™ provides Longrun™ power management technology which adjusts the voltage and clock speed of a processor in order to ensure the processor minimises the amount of time spent in idle, in which the processor is “on” but not used for processing.
A problem with such approaches however is that they are not well suited to tasks with hard deadlines, for example ensuring that a data block received by a wireless terminal is decoded by a Viterbi decoder algorithm within a set number of milliseconds. Processing execution time deadlines for certain operations in such systems are often defined by standard protocols in order that, for example the terminal can inter-operate with a base station in a wireless cellular or local area network.
Many of the tasks or operations in devices or systems such as wireless terminals operate according to one or more standards and can be implemented in a number of ways, for example by using specialised hardware accelerators such as ASIC's or by using a digital signal processor which is configured according to software. Often some of the processing or tasks overlap in time or are independent of other tasks and can therefore be performed in parallel, allowing the processing resource to allocate a slice of processing power to one task and another slice to another task. This might be achieved using multiple processors or timeslicing a resource such as a microprocessor for example.
Various methods of scheduling the processor time for a number of tasks are known in the art. Modifying such scheduling methodologies to incorporate the concept of reducing the voltage-frequency of the processing resource when dealing with certain tasks in order to reduce power consumption, is described in conceptual terms in Flavius Gruian “Hard Real-Time Scheduling for Low-Energy Using Stochastic Data and DVS processors”, ISLPED'01, Aug. 2-7, 2001. However the practical implementation of such a system is non-trivial.